Senior Embedded Software Engineer (Core&Middleware)

ABOUT THE PROJECT

Join a strategic partnership with a global leader in long-range wireless technology to architect the software ecosystem for a next-generation multi-core System-on-Chip (SoC). This engagement goes beyond standard firmware development; you will co-develop a comprehensive developer platform that transforms complex multi-core hardware into an accessible, world-class microcontroller product. By leveraging open-source real-time operating systems like Zephyr and FreeRTOS, and implementing cutting-edge hardware-enforced security frameworks (PSA Level 3, TrustZone, TEE), you will empower the global embedded community to deploy secure, ultra-low-power IoT applications. You will work within a specialized team structure to deliver a modern toolchain centered around Visual Studio Code, ensuring a seamless “edit-build-debug” experience for the next wave of wireless innovation!

YOUR ROLE

• Develop the Hardware Abstraction Layer (HAL) and low-level C drivers for a next-generation multi-core SOC architecture.
• Design and implement Inter-Processor Communication (IPC) mailbox drivers to orchestrate data exchange between Application, Protocol, and Radio cores.
• Implement the system-wide power management state machine, managing clock gating and supply assignments for ultra-low power consumption.
• Create Board Support Packages (BSPs) and Devicetree definitions to adapt the hardware to Zephyr and FreeRTOS ecosystems.
• Collaborate with the architecture team to define memory maps and interrupt routing for a complex multi-core system.
• Working directly with hardware teams.
• Ensure code compliance with unified code styles and static security analysis requirements.

REQUIREMENTS

• 5+ years of embedded software development experience with a strong focus on low-level drivers and HAL.
• Deep knowledge of ARM Cortex-M architecture and multi-core resource scheduling.
• Proficiency in C programming for real-time operating systems, specifically Zephyr and FreeRTOS.
• Experience implementing Inter-Processor Communication (IPC) mechanisms (mailboxes, spinlocks, shared memory).
• Familiarity with peripheral interfaces such as SPI, QSPI, GPIO, I2C, PWM, and ADC.
• Experience working with FPGA emulation platforms or RTL simulation environments for early software bring-up.
• Solid understanding of embedded power management, including sleep modes and wake-up sources.
• English language proficiency for technical documentation and cross-functional communication.

NICE TO HAVE

• Experience integrating software with the CMSIS layer.
• Previous involvement in developing Software Development Kits (SDKs) for public release.
• Familiarity with CMake/Kconfig build systems.